1. Field of the Invention
The present invention relates to an asynchronous transfer mode (ATM) cell multiplexing/demultiplexing apparatus for, after identifying routing information, transmitting ATM cells from a single ATM layer device to a plurality of physical layer devices and multiplexing the ATM cells transmitted from the number of physical layer devices into the single ATM layer device over a universal test and operation physical interface for ATM (UTOPIA) interface.
2. Discussion of Related Art
In an ATM system, user information is divided into predetermined-sized packets and destination information is appended to a packet header, so the user information is transmitted in fixed-length cells and then restored to the original information. The fixed-sized cell comprises a 48-byte information field and a 5-byte header. The cell header contains virtual channel and virtual path information and other control information. The user information is transmitted to a destination according to the virtual channel and path information in the cell header.
An architecture of an ATM protocol is conformable to an open systems interconnection (OSI) layer model. Each layer has its own proper function and a certain layer service is realized using a service of a layer located just below it. For the ATM protocol, a physical layer, ATM layer, and ATM adaptation layer (AAL) construct a lower layer, which performs proper ATM functions. The physical layer has a function of providing transmission resources for transmission of the ATM cells. The ATM layer generates and removes the cell header and establishes a virtual channel (VC) and virtual path (VP) of the cells, thus selecting a path. The ATM adaptation layer is located between the ATM layer and a higher layer and splits the user information in a unit of predetermined length for an adaptation to a cell construction before transmission.
This ATM system interfaces the ATM layer device and the physical layer device with respect to the ATM cells and maps them into a synchronous transfer mode (STM) frame, before transmission. The ATM layer device transmits the ATM cells to the physical layer based upon a segmentation and reassembly (SAR) interface. The physical layer device transmits the ATM cells to the ATM layer over the UTOPIA interface. A UTOPIA 1 level interface matches a single ATM layer device to a single physical layer device. A UTOPIA 2 level interface matches a single ATM layer device to a number of physical layer devices.
General functions of the ATM layer are set forth in the following description. The ATM layer device generates a header for controlling ATM cell transmission, appends it to the 48-byte information field, and transmits the header and the information field to the lower physical layer, or transmits the 48-byte information field to the higher ATM adaptation layer (ALL) after removing the header from a 53-byte cell. The ATM layer device also performs a cell multiplexing function of carrying cells generated from a plurality of virtual paths and virtual channels on a single transmission channel and a cell demultiplexing function of separating cells from a single channel and distributing them to a number of virtual paths or virtual channels.
FIG. 1 is a block diagram of a conventional ATM cell multiplexing/demultiplexing apparatus for performing ATM cell multiplexing and demultiplexing functions on the ATM layer. As shown in the drawing, the ATM cell multiplexing/demultiplexing apparatus includes: a number of demultiplexing buffers 1 to N for buffering ATM cells generated from each virtual line; a multiplexing/demultiplexing unit 10, for multiplexing the ATM cells from the demultiplexing buffers 1 to N and, for analyzing virtual path identifiers (VPI) and virtual channel identifiers of ATM cells transmitted from a multiplexing buffer 20 and demultiplexing the ATM cells into the demultiplexing buffers 1 to N; and a multiplexing buffer 20, for buffering the ATM cells multiplexed by the multiplexing/demultiplexing unit 10 and transmitting them to the physical layer device and, for receiving the ATM cells from the physical layer device.
Operation of this conventional ATM cell multiplexing/demultiplexing apparatus is described below.
The virtual lines are identified by the VCIs and VPIs and have the corresponding demultiplexing buffers 1 to N. The demultiplexing buffers 1 to N buffer the ATM cells transmitted via each virtual line and then output them according to priority of the cells in transmission. The multiplexing/demultiplexing unit 10 multiplexes the ATM cells from each demultiplexing buffer 1 to N into the multiplexing buffer 20. The multiplexing buffer 20 transmits the multiplexed ATM cells to the physical layer device, so that the cells can be transmitted to the destination.
The multiplexing buffer 20 also buffers the ATM cells from the physical layer device and transmits them to the multiplexing/demultiplexing unit 10. The multiplexing/demultiplexing unit 10 analyzes the header of the ATM cell from the multiplexing buffer 20 and determines whether or not to transmit the cell according to cell loss priority data registered in a cell loss priority field of the cell header. If the cell has important information to be transmitted, the multiplexing/demultiplexing unit 10 analyzes the VPI and VCI registered in another field of the header of the cell. If both the VPI and VCI are xe2x80x9c0xe2x80x9d, the multiplexing/demultiplexing unit 10 transmits the ATM cell to the corresponding demultiplexing buffer 1. According to such manner, the multiplexing/demultiplexing unit 10 transmits the ATM cells to the demultiplexing buffers 1 to N of each virtual line corresponding to respective, analyzed VPIs and VCIs, thereby demultiplexing the ATM cells.
This conventional ATM cell multiplexing/demultiplexing apparatus performs the multiplexing/demultiplexing operation by the VPIs and VCIs, so it must have many buffers for each and every virtual line. This makes the configuration of the apparatus complicated. In addition, the conventional ATM cell multiplexing/demultiplexing apparatus must perform access to the ATM cell header to analyze the VCI and VPI during the ATM cell multiplexing/demultiplexing operation. This results in complicated control operation, thereby increasing load on the system. Because of increment of the load caused by the complicated control operation, the multiplexing/demultiplexing operation cannot be performed for all ATM cells, resulting in decrease of performance of the system.
Accordingly, the present invention is directed to an ATM cell multiplexing/demultiplexing apparatus that substantially obviates one or more of the limitations and disadvantages of the related art.
An objective of the present invention is to provide an ATM cell multiplexing/demultiplexing apparatus for performing a UTOPIA 2 level interface function using a UTOPIA 1 level interface.
Another objective of the present invention is to provide an ATM cell multiplexing/demultiplexing apparatus for performing multiplexing and demultiplexing operation using simple routing information, thereby reducing load and time required for analysis of an ATM cell header.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure as illustrated in the written description and claims hereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the present invention as embodied and broadly described, in an asynchronous transfer mode (ATM) system having a number of physical layer devices for transmitting ATM cells at low speed and an ATM layer device for transmitting ATM cells at high speed, an ATM cell multiplexing/demultiplexing apparatus comprises: a decoding/demultiplexing unit for extracting routing information from a header of each ATM cell transmitted from the ATM layer device and demultiplexing the ATM cell according to the routing information extracted into the number of physical layer devices; an ATM cell multiplexing unit for multiplexing the ATM cells transmitted from the number of physical layer devices into the ATM layer device; a receiving routing unit for inserting routing information within a header of each ATM cell multiplexed by the ATM cell multiplexing unit; and a micro bus interface unit for interfacing the ATM layer device and the number of physical layer devices with respect to system operation and management information and transmitting an interrupt signal of each physical layer device to the ATM layer device.
The ATM cell multiplexing/demultiplexing apparatus inserts simple routing information in corresponding bits within an ATM cell and performs cell multiplexing/demultiplexing operation between a single ATM layer device and a number of physical layer devices using the routing information. In case of demultiplexing ATM cells from the high speed transmission ATM layer device into the number of low speed transmission physical layer devices over the UTOPIA interface, this apparatus extracts routing information from an ATM cell, demultiplexes the ATM cell according to the extracted routing information, and removes the routing information before transmitting the cell. Alternatively, in case of multiplexing the ATM cells from the many low speed transmission physical layer devices into the high speed ATM layer device over the UTOPIA interface, this apparatus multiplexes the ATM cells transmitted from each physical layer device and inserts within the cell header routing information indicating a corresponding physical layer device from which the cell is transmitted before transmitting the cell to the ATM layer device. This apparatus also interfaces the ATM layer device and the number of physical layer devices with respect to system operation and management information and transmits an interrupt commanding stop of cell transmission which is generated when a physical layer device cannot receive the ATM cells.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.